A RISC-V Extension for the Fresh Breeze Architecture

We report on a RISC-V extension for a novel multi-core computer organization able to execute applications with high performance and energy efficiency. Novel features of this architecture include support for data objects represented by trees of 128-byte memory chunks, and hardware implementation of task scheduling and load balancing. We call our project Fresh Breeze1 in view of its novelty and potential. User programs are written in funJava, a functional subset of the Java programming language, compiled into independent blocks of instructions called codelets, and run on an architecture model using our Kiva simulator. Extensions to the RISC-V core will consist of special instructions for creating and accessing memory chunks, and for spawning and coordinating tasks for codelet execution. Also, the core processor will include an AutoBuffer that holds memory chunks for direct access that are automatically loaded in response to read instructions. These extensions will permit us to build an FPGA Fresh Breeze prototype using the BlueDBM facility of the Computation Structures Group in theMIT Computer Science and Artificial Intelligence Laboratory.